Mapping I/O Signals: MVS-8500 with TTL I/O ModuleCognex VisionPro

This topic contains the following sections.

VisionPro reads the I/O configuration from the VisionPro.ini file in the Windows or WINNT directory. For the MVS-8504 with the TTL I/O module, make sure these lines appear in VisionPro.ini:

[CogFrameGrabber8504 #0]
IOConfig = Standard

I/O signals using the TTL I/O configuration map to physical connectors using the TTL I/O module (P/N 800-5818-1). The TTL I/O module makes available 16 bidirectional TTL lines. Four of these bidirectional TTL lines can be configured as strobes, and four can be configured as triggers.

The following figure shows how you connect I/O signals using the TTL I/O module.

Framework PhysicalIO Walkthrough 8500TTL Map 8500TTL

Mapping for the TTL I/O Module

The following table lists the physical connections to the TTL I/O module. In the table, Software line indicates the number assigned in software to the input or output. You access these software lines using CogInputLines and CogOutputLines collections. Signal name indicates the name of the hardware signal, as described in the MVS-8500 Hardware Manual. Consult that manual for a complete description of hardware signal names, connections, and installation information.

Note: The MVS-8500L frame grabber (single-channel PCI Express) provides a total of eight I/O lines. These lines are numbered 8-15. Even though the CogInputLines and CogOutputLines collections indicate the presence of 16 lines, only the upper 8 lines (values 8 through 15) can be used on the MVS-8500L.

Note that some of the input/output lines may be used by an acquisition FIFO. If you enable an output line that is used by an acquisition FIFO as one of the reserved strobe lines, the strobe will not fire unless you disable the line. Similarly if you enable an input line that is used by a FIFO as a reserved trigger line, you will not receive triggers unless you disable the line. In these cases, the input line CanBeEnabled and output line CanBeEnabled properties may return True even if the FIFO reserves the lines for itself.

Table 1. TTL I/O Module signal mapping
Software lineSignal NameTTL I/O Label
InputLines(0) and OutputLines(0)TTL_BI_0B0
InputLines(1) and OutputLines(1)TTL_BI_1B1
InputLines(2) and OutputLines(2)TTL_BI_2B2
InputLines(3) and OutputLines(3)TTL_BI_3B3
InputLines(4) and OutputLines(4)TTL_BI_4B4
InputLines(5) and OutputLines(5)TTL_BI_5B5
InputLines(6) and OutputLines(6)TTL_BI_6B6
InputLines(7) and OutputLines(7)TTL_BI_7B7
InputLines(8) and OutputLines(8)TTL_BI_8 (Trigger 1)T1
InputLines(9) and OutputLines(9)TTL_BI_9 (Strobe 1)S2
InputLines(10) and OutputLines(10)TTL_BI_10 (Trigger 2)T2
InputLines(11) and OutputLines(11)TTL_BI_11 (Strobe 2)S2
InputLines(12) and OutputLines(12)TTL_BI_12 (Trigger 3)T3
InputLines(13) and OutputLines(13)TTL_BI_13 (Strobe 3)S3
InputLines(14) and OutputLines(14)TTL_BI_14 (Trigger 4)T4
InputLines(15) and OutputLines(15)TTL_BI_15 (Strobe 4)S4
TTL groundG