# Acquisition and Results Timing Diagram

The following image shows a high level acquisition and results timing diagram:

Explanation of behaviors:

A: The PLC sets the Trigger bit to initiate an image acquisition in the vision system a short time after the bit changes from 0 to 1. This is a rising edge signal that needs to be seen in the vision system in order to trigger an image acquisition.

B: The Acquisition ID is incremented by 1 when a successful image acquisition begins and the updated value is sent to the PLC in the next IO cycle.

C: The Trigger Ready and Exposure Complete bits are set upon completion of an image acquisition. The timing can vary from the example diagram depending on the exposure settings.

D: The Results Valid bit is set when the results are available after the inspection runs on the acquired image and those results are ready for the PLC to read. It can be cleared by setting another signal from the PLC described in the How to Trigger an Inspection section.

The following image shows a detailed trigger and acquisition signals timing diagram: